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MC100LVEL56 3.3V ECL Dual Differential 2:1 Multiplexer
Description
The MC100LVEL56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. The device features both individual and common select inputs to address both data path and random logic applications. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE, The D input will bias around VCC/2 forcing the Q output LOW. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
Features
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SO-20 WB DW SUFFIX CASE 751D
MARKING DIAGRAM*
20 100LVEL56 AWLYYWWG
* * * * * * * *
580 ps Typical Propagation Delays Separate and Common Select The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V Internal Input Pulldown Resistors on D(s), SEL(s), and COM_SEL Q Output will Default LOW with Inputs Open or at VEE Pb-Free Packages are Available*
1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 11
1
Publication Order Number: MC100LVEL56/D
MC100LVEL56
COM_SEL
Table 1. PIN DESCRIPTION
PIN D0a* - D1a* SEL1 15 VCC 14 Q1 13 Q1 12 VEE 11 D0a* - D1a* D0b* - D1b* D0b* - D1b* SEL0* - SEL1* COM_SEL* VBB0, VBB1 FUNCTION ECL Input Data a ECL Input Data a Invert ECL Input Data b ECL Input Data b Invert ECL Indiv. Select Input ECL Common Select Input Output Reference Voltage ECL True Outputs ECL Inverted Outputs Positive Supply Negative Supply
VCC 20
Q0 19
Q0 18
SEL0 17
16
1
0
1
0
Q0 - Q1 Q0 - Q1 VCC VEE
1 D0a
2 D0a
3
4
VBBO D0b
5 D0b
6 7 D1a D1a
8 VBB1
9 D1b
* Pins will default LOW when left open. 10 D1b
Table 2. TRUTH TABLE
SEL0 X L L H H SEL1 X L H H L COM_SEL H L L L L Q0, Q0 a b b a a Q1, Q1 a b a a b
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 20-Lead Package (Top View) and Logic Diagram
Table 3. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 KW N/A > 2 kV > 200 V > 4 kV Level 1 UL 94 V-0 @ 0.125 in 28 to 34 147
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Oxygen Index Transistor Count Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
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MC100LVEL56
Table 4. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board t2 to 3 sec @ 248C t2 to 3 sec @ 260C SO-20 WB SO-20 WB SO-20 WB Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 to 0 -8 to 0 6 to 0 -6 to 0 50 100 0.5 -40 to +85 -65 to +150 90 60 30 to 35 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 5. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 4) Vpp < 500 mV Vpp y 500 mV Input HIGH Current Input LOW Current Dn Dn 0.5 -600 2215 1470 2135 1490 1.92 Min Typ 20 2295 1605 Max 24 2420 1745 2420 1825 2.04 2275 1490 2135 1490 1.92 Min 25C Typ 20 2345 1595 Max 24 2420 1680 2420 1825 2.04 2275 1490 2135 1490 1.92 Min 85C Typ 20 2345 1595 Max 24 2420 1680 2420 1825 2.04 Unit mA mV mV mV mV V
1.3 1.5
2.9 2.9 150
1.2 1.4
2.9 2.9 150
1.2 1.4
2.9 2.9 150
V V mA mA mA
IIH IIL
0.5 -600
0.5 -600
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 3. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP(min) and 1 V.
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MC100LVEL56
Table 6. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = -3.3 V (Note 5)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 7) Vpp < 500 mV Vpp y 500 mV Input HIGH Current Input LOW Current Dn Dn 0.5 -600 -1085 -1830 -1165 -1810 -1.38 Min Typ 20 -1005 -1695 Max 24 -880 -1555 -880 -1475 -1.26 -1025 -1810 -1165 -1810 -1.38 Min 25C Typ 20 -955 -1705 Max 24 -880 -1620 -880 -1475 -1.26 -1025 -1810 -1165 -1810 -1.38 Min 85C Typ 20 -955 -1705 Max 24 -880 -1620 -880 -1475 -1.26 Unit mA mV mV mV mV V
-2.0 -1.8
-0.4 -0.4 150
-2.1 -1.9
-0.4 -0.4 150
-2.1 -1.9
-0.4 -0.4 150
V V mA mA mA
IIH IIL
0.5 -600
0.5 -600
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 6. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
Table 7. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = -3.3 V (Note 8)
-40C Symbol fmax tPLH tPHL Characteristic Maximum Toggle Frequency (See Figure 2, Fmax/JITTER) Propagation Delay to Output D SEL COMSEL 400 430 430 40 600 730 730 80 100 1.5 150 200 1000 540 150 200 1000 540 150 200 1000 540 420 440 440 Min Typ Max Min 25C Typ 1 Max Min 85C Typ Max Unit GHz ps
440 40
620 740 740 80 100
440 450 450 40
640 750 750 80 100
tSKEW tSKEW tJITTER VPP tr tf
Within-Device Skew (Note 9) Duty Cycle Skew (Note 10) Random Clock Jitter (RMS) Input Swing (Note 11) Output Rise/Fall Times Q (20% - 80%)
ps ps ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. VEE can vary 0.3 V. 9. Within-device skew is defined as identical transitions on similar paths through a device. 10. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 11. VPP(min) is minimum input swing for which AC parameters are guaranteed.
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MC100LVEL56
1000 OUTPUT VOLTAGE (mV amplitude) 900 800 700 600 500 400 300 200 100 0 0 (JITTER) 10 9 8 JITTER (ps RMS) 7 6 5 4 3 2 1 500 750 1000 1250 1500 1750 2000
250
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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MC100LVEL56
ORDERING INFORMATION
Device MC100LVEL56DW MC100LVEL56DWG MC100LVEL56DWR2 MC100LVEL56DWR2G Package SO-20 WB SO-20 WB (Pb-Free) SO-20 WB SO-20 WB (Pb-Free) Shipping 38 Units / Rail 38 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100LVEL56
PACKAGE DIMENSIONS
SO-20 WB DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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L
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MC100LVEL56/D

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